LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.ALL;

ENTITY arith_unit IS
	PORT ( 	a: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			sel: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
			cin: IN STD_LOGIC;
			y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END arith_unit ;

ARCHITECTURE arith_unit OF arith_unit IS
BEGIN
	arith_unit: PROCESS (a,b,sel)
	BEGIN	
		CASE sel IS
			WHEN "0000" =>
				--transfer a
				y <= a;
			WHEN "0001" =>
				--increment a
				y <=  CONV_STD_LOGIC_VECTOR(CONV_INTEGER(a)+1,8);
			WHEN "0010" =>
				-- decrement a
				y <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(a)-1,8);
			WHEN "1100" =>
				-- transfer b
				y <= b;
			WHEN "0100" =>
				-- increment b
				y <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(b)+1,8);
			WHEN "0101" =>
				-- decrement b
				y <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(b)-1,8);
			WHEN "1110" =>
				-- add a and b
				y <= a+b;
			WHEN "1111" =>
				-- add a and b and carry
				y <= a+b+cin;
			WHEN OTHERS =>
				y <=a;
		END CASE;
	END PROCESS;
		
END arith_unit;